View S3C9454_1123790.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

s3c9442/c9444/f9444/c9452/c9454/f9454 product overview 1- 1 1 product overview sam88rcri product family samsung's sam88rcri family of 8-bit single-chip cmos microcontrollers offers a fast and efficient cpu, a wide range of integrated peripherals, and various mask-programmable rom sizes. a address/data bus architecture and a large number of bit-configurable i/o ports provide a flexible programming environment for applications with varied memory and i/o requirements. timer/counters with selectable operating modes are included to support real-time operations. s3c9442/c9444/c9452/c9454 microcontroller the s3c9442/c9444/c9452/c9454 single-chip 8-bit microcontroller is designed for useful a/d converter , sio application field. the s3c9442/c9444/c9452/c9454 uses powerful sam88rcri cpu and s3c9442/c9444/c9452/c9454 architecture. the internal register file is logically expanded to increase the on- chip register space. the s3c9442/c9444/c9452/c9454 has 2k/4k bytes of on-chip program rom and 208 bytes of ram. the s3c9442/c9444/c9452/c9454 is a versatile general-purpose microcontroller that is ideal for use in a wide range of electronics applications requiring simple timer/counter, pwm. in addition, the s3c9442/c9444/c9452/c9454?s advanced cmos technology provides for low power consumption and wide operating voltage range. using the sam88rcri design approach, the following peripherals were integrated with the sam88rcri core: ? three configurable i/o ports (18 pins) ? four interrupt sources with one vector and one interrupt level ? one 8-bit timer/counter with time interval mode ? analog to digital converter with nine input channels and 10-bit resolution ? one 8-bit pwm output the s3c9442/c9444/c9452/c9454 microcontroller is ideal for use in a wide range of electronic applications requiring simple timer/counter, pwm, adc. s3c9452/c9454 is available in a 20/16-pin dip and a 20-pin sop package. s3c9452/c9454 is available in a 8-pin and a 8-pin sop package. mtp the s3f9444/f9454 is an mtp (multi time programmable) version of the s3c9442/c9444/c9452/c9454 microcontroller. the s3f9444/f9454 has on-chip 4-kbyte multi-time programmable flash rom instead of masked rom. the s3f9444/f9454 is fully compatible with the s3c9442/c9444/c9452/c9454, in function, in d.c. electrical characteristics and in pin configuration.
product overview s3c9442/c9444/f9444/c9452/c9454/f9454 1- 2 features cpu ? sam88rcri cpu core ? the sam88rcri core is low-end version of the current sam87 core. memory ? 2/4-kbyte internal program memory ? 208-byte general purpose register area instruction set ? 41 instructions ? the sam88rcri core provides all the sam87 core instruction except the word-oriented instruction, multiplication, division, and some one-byte instruction. instruction execution time ? 400 ns at 10 mhz f osc (minimum) interrupts ? 4 interrupt sources with one vector ? one interrupt level general i/o ? three i/o ports (max 18 pins) ? bit programmable ports 8-bit high-speed pwm ? 8-bit pwm 1-ch (max: 156 khz) ? 6-bit base + 2-bit extension built-in reset circuit ? low voltage detector for safe reset timer/counters ? one 8-bit basic timer for watchdog function ? one 8-bit timer/counter with time interval modes a/d converter ? nine analog input pins ? 10-bit conversion resolution oscillation frequency ? 1 mhz to 10 mhz external crystal oscillator ? maximum 10 mhz cpu clock ? internal rc: 3.2 mhz ( typ.), 0.5 mhz ( typ.) in v dd = 5 v operating temperature range ? ? 40 c to + 85 c operating voltage range ? 2.0 v (lvr level) to 5.5 v smart option package types ? s3c9452/c9454: ? 20-dip-300a ? 20-sop-375 ? 16-dip-300a ? s3c9442/c9444 ? 8-dip-300 ? 8-sop-225
s3c9442/c9444/f9444/c9452/c9454/f9454 product overview 1- 3 block diagram 88rcri samri cpu port i/o and interrupt control 2 kb rom 4 kb rom 208 byte register file timer 0 adc pwm x in x out osc basic timer adc0-adc8 p0.6/pwm port 0 port 2 port 1 p0.0/adc0/int0 p0.1/adc1/int1 p0.2/adc2 p0.7/adc7 ... p1.0 p1.1 p1.2 p2.0/t0 p2.1 p2.6 ... note: p1.2 is used as input only figure 1-1. block diagram
product overview s3c9442/c9444/f9444/c9452/c9454/f9454 1- 4 pin assignments s3c9452/c9454 (20-dip-300a/ 20-sop-375) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 v ss x in /p1.0 x out /p1.1 reset /p1.2 p2.0/t0 p2.1 p2.2 p2.3 p2.4 p2.5 v dd p0.0/adc0/int0 p0.1/adc1/int1 p0.2/adc2 p0.3/adc3 p0.4/adc4 p0.5/adc5 p0.6/adc6/pwm p0.7/adc7 p2.6/adc8/clo figure 1-2. pin assignment diagram (20-pin dip/sop package)
s3c9442/c9444/f9444/c9452/c9454/f9454 product overview 1- 5 s3c9452/c9454 (16-dip-300a) v dd p0.0/adc0/int0 p0.1/adc1/int1 p0.2/adc2 p0.3/adc3 p0.4/adc4 p0.5/adc5 p0.6/adc6/pwm 16 15 14 13 12 11 10 9 v ss x in /p1.0 x out /p1.1 reset /p1.2 p2.0/t0 p2.1 p2.2 p2.3 1 2 3 4 5 6 7 8 figure 1-3. pin assignment diagram (16-pin dip package) s3c9442/c9444 (8-dip-300 8-sop-225) v dd p0.0/adc0/int0 p0.1/adc1/int1 p0.2/adc2 8 7 6 5 v ss x in /p1.0 x out /p1.1 reset /p1.2 1 2 3 4 figure 1-4. pin assignment diagram (8-pin dip/sop package)
product overview s3c9442/c9444/f9444/c9452/c9454/f9454 1- 6 pin descriptions table 1-1. s3c9452/c9454 pin descriptions pin name in/out pin description pin type share pins p0.0?p0.7 i/o bit-programmable i/o port for schmitt trigger input or push-pull output. pull-up resistors are assignable by software. port0 pins can also be used as a/d converter input, pwm output or external interrupt input. e-1 adc0?adc7 int0/int1 pwm p1.0?p1.1 i/o bit-programmable i/o port for schmitt trigger input or push-pull , o pen-drain output. pull-up resistors or pull-down resistors are assignable by software. e-2 x in, x out p1.2 i schmitt trigger input port b reset p2.0?p2.6 i/o bit-programmable i/o port for schmitt trigger input or push-pull, o pen-drain output. pull-up resistors are assignable by software. e e-1 ? adc8/clo t0 x in, x out ? crystal/ceramic, or rc oscillator signal for s ystem clock. p1.0?p1.1 reset i internal lvr or external reset b p1.2 v dd, v ss ? voltage input pin and ground ? clo o system clock output port e-1 p2.6 int0?int1 i external interrupt input port e-1 p0.0, p0.1 pwm o 8-bit high speed pwm output e-1 p0.6 t0 o timer0 match output e-1 p2.0 adc0?adc8 i a/d converter input e-1 e p0.0?p0.7 p2.6
s3c9442/c9444/f9444/c9452/c9454/f9454 product overview 1- 7 pin circuits v dd in n-channel p-channel figure 1-5. pin circuit type a in figure 1-6. pin circuit type b v dd out output disable data figure 1-7. pin circuit type c i/o output disable data circuit type c pull-up enable v dd digital input figure 1-8. pin circuit type d
product overview s3c9442/c9444/f9444/c9452/c9454/f9454 1- 8 v dd i/o digital input p-ch v dd open-drain enable pull-up enable analog input enable adc output disable (input mode) data m u x alternative output p2.x p2conh p2conl n-ch figure 1-9. pin circuit type e v dd i/o digital input p-ch v dd pull-up enable output disable (input mode) data m u x alternative output p0.x p0conh n-ch analog input enable adc interrupt input figure 1-10. pin circuit type e-1
s3c9442/c9444/f9444/c9452/c9454/f9454 product overview 1- 9 v dd i/o x in x out v dd open-drain enable output disable (input mode) p1.x digital input pull-up enable pull-down enable figure 1-11. pin circuit type e-2
s3c9442/c9444/f9444/c9452/c9454/f9454 e lectrical data 13- 1 13 electrical data overview in this section, the following s3c9442/c9444/c9452/c9454 electrical characteristics are presented in tables and graphs: ? absolute maximum ratings ? d.c. electrical characteristic s ? a.c. electrical characteristics ? input timing measurement points ? oscillator characteristics ? oscillation stabilization time ? operating voltage range ? schmitt trigger input characteristics ? data retention supply voltage in stop mode ? stop mode release timing when initiated by a reset ? a/d converter electrical characteristics ? lvr circuit characteristics ? lvr reset timing
electrical data s3c 9442/c9444/f9444/c9452/c9454/f9454 13- 2 table 13-1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i all ports ? 0.3 to v dd + 0.3 v output voltage v o all output ports ? 0.3 to v dd + 0.3 v output current high i oh one i/o pin active ? 25 ma all i/o pins active ? 80 output current low i ol one i/o pin active + 30 ma all i/o pins active + 150 operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c
s3c9442/c9444/f9444/c9452/c9454/f9454 e lectrical data 13- 3 table 13-2. dc electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit input high voltage v ih1 ports 0, 1, 2 and reset v dd = 2.0 to 5.5 v 0.8 v dd ? v dd v v ih2 x in and x out v dd - 0.1 input low voltage v il1 ports 0, 1, 2 and reset v dd = 2.0 to 5.5 v ? ? 0.2 v dd v v il2 x in and x out 0.1 output high voltage v oh i oh = ? 10 ma ports 0, 1, 2 v dd = 4.5 to 5.5 v v dd -1.5 v dd - 0.4 ? v output low voltage v ol i ol = 25 ma port 0, 1, and 2 v dd = 4.5 to 5.5 v ? 0.4 2.0 v input high leakage current i lih1 all input except i lih2 v in = v dd ? ? 1 ua i lih2 x in , x out v in = v dd 20 input low leakage current i lil1 all input except i lil2 and reset v in = 0 v ? ? ?1 ua i lil2 x in , x out v in = 0 v ?20 output high leakage current i loh all output pins v out = v dd ? ? 2 ua output low leakage current i lol all output pins v out = 0 v ? ? ?2 ua pull-up resistors r p v in = 0 v ports 0, 1, 2 v dd = 5 v 25 50 100 k w pull-down resistors r p v in = 0 v ports 1 v dd = 5 v 25 50 100 supply current i dd1 run mode 10 mhz cpu clock v dd = 4.5 to 5.5 v ? 5 10 ma 3 mhz cpu clock v dd = 2.0 v 2 5 i dd2 idle mode 10 mhz cpu clock v dd = 4.5 to 5.5 v ? 2 4 3 mhz cpu clock v dd = 2.0 v 0.5 1.5 i dd3 stop mode v dd = 4.5 to 5.5 v (lvr disable) ? 0.1 5 ua v dd = 4.5 to 5.5 v (lvr enable) 100 200 v dd = 2.6 v (lvr enable) 30 60 note: in stop (i dd3 ), idle (i dd2 ) current, current by adc module is not included.
electrical data s3c 9442/c9444/f9444/c9452/c9454/f9454 13- 4 table 13-3. ac electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit interrupt input low width t intl int0, int1 v dd = 5 v 10 % ? 200 ? ns reset input low width t rsl input v dd = 5 v 10 % ? 1 ? us t intl t inth x in 0.8 v dd 0.2 v dd figure 13-1. input timing measurement points
s3c9442/c9444/f9444/c9452/c9454/f9454 e lectrical data 13- 5 table 13-4. oscillator characteristics (t a = ? 40 c to + 85 c) oscillator clock circuit test condition min typ max unit main crystal or ceramic x in x out c1 c2 v dd = 4.5 to 5.5 v 1 ? 10 mhz v dd = 2.7 to 4.5 v 1 ? 6 mhz v dd = 2.0 to 2.7 v 1 ? 3 mhz external clock (main system) x in x out v dd = 4.5 to 5.5 v 1 ? 10 mhz v dd = 2.7 to 4.5 v 1 ? 6 mhz v dd = 2.0 to 2.7 v 1 ? 3 mhz external rc oscillator ? v dd = 4.75 to 5.25 v tolerance:10 % ? 4 ? mhz internal rc v dd = 4.75 to 5.25 v 3.2 oscillator 0.5 table 13-5. oscillation stabilization time (t a = - 40 c to + 85 c, v dd = 3.0 v to 5.5 v) oscillator test condition min typ max unit main crystal f osc > 1.0 mhz ? ? 20 ms main ceramic oscillation stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 10 ms external clock (main system) x in input high and low width (t xh , t xl ) 25 ? 500 ns oscillator stabilization t wait when released by a reset (1) ? 2 16 /f osc ? ms wait time t wait when released by an interrupt (2) ? ? ? ms notes: 1. f osc is the oscillator frequency. 2. the duration of the oscillator stabilization wait time, t wait , when it is released by an interrupt is determined by the settings in the basic timer control register, btcon.
electrical data s3c 9442/c9444/f9444/c9452/c9454/f9454 13- 6 10 mhz cpu clock 6 mhz 1 mhz 1 2 3 4 5 6 7 supply voltage (v) 2 mhz 3 mhz 4 mhz 2.7 5.5 4.5 figure 13-2. operating voltage range v ss a a = 0.2 v dd b = 0.4 v dd c = 0.6 v dd d = 0.8 v dd v dd v out v in b c d 0.3 v dd 0.7 v dd figure 13-3. schmitt trigger input characteristics diagram
s3c9442/c9444/f9444/c9452/c9454/f9454 e lectrical data 13- 7 table 13-6. data retention supply voltage in stop mode (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit data retention supply voltage v dddr stop mode 2.0 ? 5.5 v data retention supply current i dddr stop mode; v dddr = 2.0 v ? 0.1 5 ua note: supply current does not include current drawn through internal pull-up resistors or external output current loads. data retention mode v dddr execution of stop instrction v dd normal operating mode oscillation stabilization time stop mode t wait reset reset occurs note: t wait is the same as 4096 x 16 x 1/f osc ~ ~ ~ ~ figure 13-4. stop mode release timing when initiated by a reset
electrical data s3c 9442/c9444/f9444/c9452/c9454/f9454 13- 8 table 13-7. a/d converter electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.7 v to 5.5 v, v ss = 0 v) parameter symbol test conditions min typ max unit total accuracy ? v dd = 5.12 v cpu clock = 10 mhz v ss = 0 v ? ? 3 lsb integral linearity error ile 2 ? ? 2 differential linearity error dle 2 ? ? 1 offset error of top eot 2 ? 1 3 offset error of bottom eob 2 ? 1 2 conversion time (1) t con f osc = 10 mhz ? 20 ? m s analog input voltage v ian ? v ss ? v dd v analog input impedance r an ? 2 ? ? m w analog input current i adin v dd = 5 v ? ? 10 m a analog block current (2) i adc v dd = 5 v ? 1 3 ma v dd = 3 v 0.5 1.5 v dd = 5 v power down mode ? 100 500 na notes: 1. ?conversion time? is the time required from the moment a conversion operation starts until it ends. 2. i adc is operating current during a/d conversion.
s3c9442/c9444/f9444/c9452/c9454/f9454 e lectrical data 13- 9 table 13-8. lvr circuit characteristics (t a = 25 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit low voltage reset v lvr ? ? 2.3 3.0 3.9 v lvr hysteresis voltage v hys ? 0.3 ? v power supply voltage rise time t r 10 (note) us power supply voltage off time t off 0.5 s note: 2 16 / fx ( = 6.55 ms at fx = 10 mhz) v dd v lvr,max v hys v hys v lvr v lvr,min t off t r figure 13-5. lvr reset timing
s3c9442/c9444/f9444/c9452/c9454/f9454 me chanical data 14- 1 14 mechanical data overview the s3c9452/c9454 is available in a 20-pin dip package ( samsung: 20-dip-300a), a 20-pin sop package ( samsung: 20-sop-375), a 16-pin dip package ( samsung: 16-dip-300a). package dimensions are shown in figure 15-1, 15-2, and 15-3. the s3c9442/c9444 is available in a 8-pin dip package (samsung 8-dip-300a), a 8-pin sop package (samsung 8-sop-225). package dimensions are shown in figure 14-4 and 14-5. note : dimensions are in millimeters. 26.80 max 26.40 0 .20 (1.77) 20-dip-300a 6.40 0 .20 #20 #1 0.46 0.10 1.52 0.10 #11 #10 0-15 0.25 + 0.10 - 0.05 7.62 2.54 0.51 min 3.30 0.30 3.25 0.20 5.08 max figure 14-1. 20-dip-300a package dimensions
mechanical data s3c9 442/c9444/f9444/c9452/c9454/f9454 14- 2 note : dimensions are in millimeters. 20-sop-375 10.30 0 .30 #11 #20 #1 #10 13.14 max 12.74 0 .20 (0.66) 0-8 0.203 + 0.10 - 0.05 9.53 7.50 0.20 0.85 0.20 0.05 min 2.30 0.10 2.50 max 0.40 0.10 max + 0.10 - 0.05 1.27 figure 14-2. 20-sop-375 package dimensions
s3c9442/c9444/f9444/c9452/c9454/f9454 me chanical data 14- 3 note : dimensions are in millimeters. 19.80 max 19.40 0 .20 (0.81) 6.40 0 .20 #16 #1 16-dip-300a 0.46 0.10 1.50 0.10 #9 #8 0-15 0.25 + 0.10 - 0.05 7.62 2.54 0.38 min 3.30 0.30 3.25 0.20 5.08 max figure 14-3. 16-dip-300a package dimensions
mechanical data s3c9 442/c9444/f9444/c9452/c9454/f9454 14- 4 note : dimensions are in millimeters. 9.60 max 9.20 0 .20 2.54 0.46 0.10 1.52 0.10 (0.79) 0.33 min 3.30 0.30 3.40 0.20 5.08 max 0-15 0.25 + 0.10 - 0.05 7.62 8-dip-300 6.40 0 .20 #8 #1 #5 #4 figure 14-4. 8-dip-300 package dimensions
s3c9442/c9444/f9444/c9452/c9454/f9454 me chanical data 14- 5 note : dimensions are in millimeters. 8-sop-225 6.00 0 .30 #5 #8 #1 #4 5.13 max 4.92 0 .20 (0.56) 1.27 0.1-0.25 min 1.55 0.20 1.80 max 0.41 0.10 0-8 0.15 + 0.10 - 0.05 5.72 3.95 0.20 0.50 0.20 0.10 max figure 14-5. 8-sop-225 package dimensions
s3c9442/c9444/f9444/c9452/c9454/f9454 s3 f9444/f9454 mtp 15- 1 15 s3f9444/f9454 mtp overview the s3f9444/f9454 single-chip cmos microcontroller is the mtp (multi time programmable) version of the s3c9442/c9444/c9452/c9454 microcontroller. it has an on-chip flash rom instead of masked rom. the flash rom is accessed by serial data format. the s3f9444/f9454 is fully compatible with the s3c9442/c9444/c9452/c9454, in function, in d.c. electrical characteristics, and in pin configuration. because of its simple programming requirements, the s3f9444/f9454 is ideal for use as an evaluation chip for the s3c9442/c9444/c9452/c9454. v dd / v dd p0.0/adc0/int0/ scl p0.1/adc1/int1/ sda p0.2/adc2 p0.3/adc3 p0.4/adc4 p0.5/adc5 p0.6/adc6/ pwm p0.7/adc7 p2.6/adc8/clo s3f9454 20 19 18 17 16 15 14 13 12 11 v ss /v ss x in /p1.0 x out /p1.1 v pp / reset /p1.2 t0/p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 1 2 3 4 5 6 7 8 9 10 note: the bolds indicate mtp pin name. figure 15-1. pin assignment diagram (20-pin package)
s3f9444/f9454 mtp s3 c9442/c9444/f9444/c9452/c9454/f9454 15- 2 s3f9454 v dd / v dd p0.0/adc0/int0/ scl p0.1/adc1/int1/ sda p0.2/adc2 p0.3/adc3 p0.4/adc4 p0.5/adc5 p0.6/adc6/ pwm 16 15 14 13 12 11 10 9 v ss /v ss x in /p1.0 x out /p1.1 v pp / reset /p1.2 t0/p2.0 p2.1 p2.2 p2.3 1 2 3 4 5 6 7 8 note: the bolds indicate mtp pin name. figure 15-2. pin assignment diagram (16-pin package) s3f9444 v dd / v dd p0.0/adc0/int0/ scl p0.1/adc1/int1/ sda p0.2/adc2 8 7 6 5 v ss /v ss x in /p1.0 x out /p1.1 v pp / reset /p1.2 1 2 3 4 note: the bolds indicate mtp pin name. figure 15-3. pin assignment diagram (8-pin package)
s3c9442/c9444/f9444/c9452/c9454/f9454 s3 f9444/f9454 mtp 15- 3 table 15-1. descriptions of pins used to read/write the flash rom main chip during programming pin name pin name pin no. i/o function p0.1 sda 18 (20-pin) 14 (16-pin) i/o serial data pin (output when reading, input when writing) input and push-pull output port can be assigned p0.0 scl 19 (20-pin) 15 (16-pin) i serial clock pin (input only pin) reset , p1.2 v pp 4 i power supply pin for flash rom cell writing (indicates that mtp enters into the writing mode). when 12.5 v is applied, mtp is in writing mode and when 5 v is applied, mtp is in reading mode. (option) v dd /v ss v dd /v ss 20 (20-pin), 16 (16-pin) 1 (20-pin), 1 (16-pin) i logic power supply pin. table 15-2. comparison of s3f9444/f9454 and s3c9442/c9444/c9452/c9454 features characteristic s3f9444/f9454 s3c9442/c9444/c9452/c9454 program memory 4 kbyte flash rom 2k/4k byte mask rom operating voltage (v dd ) 2.0 v to 5.5 v 2.0 v to 5.5 v otp programming mode v dd = 5 v, v pp = 12.5 v pin configuration 20 dip/20 sop/16 dip/8 dip/8 sop eprom programmability user program multi time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp pin of the s3f9444/f9454 flash rom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 15-3 below. table 15-3. operating mode selection criteria v dd v pp reg/ mem address (a15?a0) r/w mode 5 v 5 v 0 0000h 1 flash rom read 12.5 v 0 0000h 0 flash rom program 12.5 v 0 0000h 1 flash rom verify 12.5 v 1 0e3fh 0 flash rom read protection note: "0" means low level; "1" means high level.

▲Up To Search▲

Price & Availability of S3C9454

	To Download S3C9454 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .